The present relates to a display system and more particularly to a display system having an improved architecture for a graphics processor utilizing a single-port RAM.
Known display systems include a display controller driving a display having a matrix of pixels at a fixed refresh rate. The display controller drives the pixels based upon information stored in RAM or VRAM. Typically, between 4 and 32 bits of information are associated with each pixel in the display. The display controller is also a graphics processor which receives information, such as text or graphics-information, indicating text or graphics to be rendered and written into the RAM. After the text and graphics are written into the RAM, the display controller reads the rendered information from the RAM and activates the pixels in the display accordingly.
In order to reduce cost, a single-port RAM may be utilized. The single-port RAM cannot be written to and read from simultaneously. Further, the display controller will be accessing the RAM at a certain rate to maintain the refresh rate. Therefore, the amount of text and graphics which can be rendered and written to RAM in a given period of time is limited. As a result, there may be periods of significant delay before a large amount of text or graphics appear on the display.
The present invention provides a display system having a display controller which utilizes a single-port RAM. The display controller, based upon graphics and text codes from an external source, such as CPU, renders text and/or graphics and writes this information to the RAM. The display controller also reads information from the RAM and activates pixels on display based upon the information in the RAM.
Generally, the display controller reads from the RAM and activates pixels in the display at a constant refresh rate. However, when the number of text and/or graphics to be rendered by the display controller exceeds a predetermined threshold or has been delayed for a predetermined time period, the display controller reduces the refresh rate of the display, thereby permitting the display controller to render the text and/or graphics and write the rendered information to the RAM. When the display controller renders the text and/or graphics which have accumulated, the display controller returns to the original, higher refresh rate.
In this manner, a single port RAM can be utilized without significant reduction in display quality. The temporary reduction in refresh rate will be less noticeable than a significant delay in graphics and text rendering.